Please use this identifier to cite or link to this item: http://dspace2020.uniten.edu.my:8080/handle/123456789/5303
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dc.contributor.authorEndut, Z.
dc.contributor.authorAhmad, I.
dc.contributor.authorSwee, G.L.H.
dc.contributor.authorSukemi, N.M.
dc.date.accessioned2017-11-15T02:57:24Z-
dc.date.available2017-11-15T02:57:24Z-
dc.date.issued2006
dc.identifier.urihttp://dspace.uniten.edu.my:80/jspui/handle/123456789/5303-
dc.description.abstractIn this paper, the failure mode and solder bump strength for low-k flip chip devices were determined using die pull technique. The results show there is no significant difference between low-k and non low-k devices in terms of bumps strength for the amount of taffy in this device. However, there is different in failure mode which shows an increasing in VRO and SRO failure mode. Die pull test within a time and bake factor also help to minimize VRO and SRO failure mode. However, VRO and SRO failure mode were expected as an another impact of low-k materials on flip chip packaging. ©2006 IEEE.
dc.titleImpact of low-k devices on failure mode of flip chip tensile pull test
item.fulltextNo Fulltext-
item.grantfulltextnone-
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