Please use this identifier to cite or link to this item: http://dspace2020.uniten.edu.my:8080/handle/123456789/5212
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMaheran, A.H.A.
dc.contributor.authorNoor Faizah, Z.A.
dc.contributor.authorMenon, P.S.
dc.contributor.authorAhmad, I.
dc.contributor.authorApte, P.R.
dc.contributor.authorKalaivani, T.
dc.contributor.authorSalehuddin, F.
dc.date.accessioned2017-11-15T02:56:39Z-
dc.date.available2017-11-15T02:56:39Z-
dc.date.issued2014
dc.identifier.urihttp://dspace.uniten.edu.my:80/jspui/handle/123456789/5212-
dc.description.abstractThe evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction. © 2014 IEEE.
dc.titleStatistical process modelling for 32nm high-K/metal gate PMOS device
item.fulltextNo Fulltext-
item.grantfulltextnone-
Appears in Collections:COE Scholarly Publication
Show simple item record

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.