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http://dspace2020.uniten.edu.my:8080/handle/123456789/5196Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Maheran, A.H.A. | |
| dc.contributor.author | Menon, P.S. | |
| dc.contributor.author | Shaari, S. | |
| dc.contributor.author | Ahmad, I. | |
| dc.contributor.author | Faizah, Z.A.N. | |
| dc.date.accessioned | 2017-11-15T02:56:30Z | - |
| dc.date.available | 2017-11-15T02:56:30Z | - |
| dc.date.issued | 2015 | |
| dc.identifier.uri | http://dspace.uniten.edu.my:80/jspui/handle/123456789/5196 | - |
| dc.description.abstract | This paper aims to study the effect of process parameter variation on a nano-scaled planar p-type MOSFET (metal-oxide-semiconductor field-effect transistor) device for 22 nm technology using Taguchi's L9 orthogonal array. The device was constructed with high-k/metal gate consisting of Titanium dioxide (TiO2) and Tungsten silicide (WSix) metal gate using an industrial-based numerical simulator. Using Taguchi's Signal-to-noise ratio (SNR) of nominal-the-best (NTB), the compensation implantation has been as identified as the dominant factor influencing the Vth value with 67.77% while the Halo implantation tilting angle has been identified as the adjustment factor. Upon optimization, the Vth value is-0.29538 V which is within the requirements of the International Technology Roadmap for Semiconductors (ITRS) 2012 which is-0.289 V ± 12.7 %. © 2015 IEEE. | |
| dc.title | Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method | |
| item.fulltext | No Fulltext | - |
| item.grantfulltext | none | - |
| Appears in Collections: | COE Scholarly Publication | |
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